ISSN:
1573-1979
Schlagwort(e):
latch-up
;
smart power
;
CMOS technology
;
design methodology
Quelle:
Springer Online Journal Archives 1860-2000
Thema:
Elektrotechnik, Elektronik, Nachrichtentechnik
Notizen:
Abstract To answer to the need of a cost effective smart power technology, an original design methodology that permits implementing latch-up free smart power circuits on a very simple CMOS/DMOS technology is proposed. The basic concept used to this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up. The efficiency of the design methodology is experimentally shown.
Materialart:
Digitale Medien
URL:
http://dx.doi.org/10.1007/BF01240836
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