ISSN:
1573-7640
Keywords:
CONTROL FLOW
;
IF-CONVERSION
;
INSTRUCTION SCHEDULING
;
PREDICATED EXECUTION
;
REVERSE IF-CONVERSION
Source:
Springer Online Journal Archives 1860-2000
Topics:
Computer Science
Notes:
Abstract Predicated execution is a promising architectural feature for exploiting instruction-level parallelism in the presence of control flow. Compiling for predicated execution involves converting program control flow into conditional, or predicated, instructions. This process is known as if-conversion. In order to apply ifconversion effectively, one must address two major issues: what should be ifconverted and when the if-conversion should be performed. A compiler's use of predication as a representation is most effective when large amounts of code are if-converted and when if-conversion is performed early in the compilation procedure. On the other hand, efficient execution of code generated for a processor with predicated execution requires a delicate balance between control flow and predication. The appropriate balance is tightly coupled with scheduling decisions and detailed processor characteristics. This paper presents a compilation framework based on partial reverse if-conversion that allows the compiler to maximize the benefits of predication as a compiler representation while delaying the final balancing of control flow and predication to schedule time.
Type of Medium:
Electronic Resource
URL:
http://dx.doi.org/10.1023/A:1018787007582
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