ISSN:
1433-299X
Keywords:
Hardware verification
;
Fault tolerance
;
Protocol verification
;
Clock synchronization
;
Manchester format
;
Automatic theorem proving
;
Boyer-Moore logic
;
ISO protocol level 1
;
Performance modeling
Source:
Springer Online Journal Archives 1860-2000
Topics:
Computer Science
Notes:
Abstract We present a formal model of asynchronous communication between two digital hardware devices. The model takes the form of a function in the Boyer-Moore logic. The function transforms the signal stream generated by one processor into that consumed by an independently clocked processor, given the phases and rates of the two clocks and the communications delay. The model can be used quantitatively to derive concrete performance bounds on communications at ISO protocol level 1 (physical level). We use the model to show that an 18-bit/cell biphase mark protocol reliably sends messages of arbitrary length between two processors provided the ratio of the clock rates is within 5% of unity.
Type of Medium:
Electronic Resource
URL:
http://dx.doi.org/10.1007/BF01211081
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