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  • 68.55  (2)
  • 68.55.Df  (1)
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  • 1
    Electronic Resource
    Electronic Resource
    MOS transistors with epitaxial Si, laterally grown over SiO2 by liquid phase epitaxy (1992)
    Springer
    Applied physics 54 (1992), S. 103-105 
    Details
    ISSN: 1432-0630
    Keywords: 68.55 ; 73.40T ; 85.30D
    Source: Springer Online Journal Archives 1860-2000
    Topics: Mechanical Engineering, Materials Science, Production Engineering, Mining and Metallurgy, Traffic Engineering, Precision Mechanics , Physics
    Notes: Abstract We describe the first MOS transistors fabricated in silicon-on-insulator layers, obtained by liquid phase epitaxial lateral overgrowth of Si over SiO2. Growth is performed around 930°–920° C using indium as a solvent. The layers are therefore p-type and have a doping of 4·1016 cm−3. Electron mobilities of 540 cm2/Vs are obtained in the inversion channel; the threshold voltage of transistors with a gate length of 14.1 μm is 510 mV. Our data demonstrate the applicability of liquid-phase epitaxial Si grown over oxidized Si for future use in three-dimensional integrated-device processing.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00348140
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    Paper (German National Licenses)
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  • 2
    Electronic Resource
    Electronic Resource
    The coalescence of silicon layers grown over SiO2 by liquid-phase epitaxy (1993)
    Springer
    Applied physics 57 (1993), S. 249-254 
    Details
    ISSN: 1432-0630
    Keywords: 68.55.Df ; 73.40.Ty
    Source: Springer Online Journal Archives 1860-2000
    Topics: Mechanical Engineering, Materials Science, Production Engineering, Mining and Metallurgy, Traffic Engineering, Precision Mechanics , Physics
    Notes: Abstract We have investigated by liquid-phase epitaxy (LPE) the coalescence of defect-free silicon-on-insulator (SOI) layers. The SOI lamellae grow out laterally from neighbouring seeding windows and spread over the SiO2. In our study, the seeding window edges are straight. The long window edges are parallel and extend in the (111) substrate plane in $$[11\bar 2]$$ direction. Coalescence of SOI lamellae takes place without the formation of defects whenever it begins at one point and then proceeds in directions parallel to the longer edges of the windows in a “zip”-like mechanism. Defect-free coalescence seams reach lengths of up to 150 μm.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00332598
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    Paper (German National Licenses)
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  • 3
    Electronic Resource
    Electronic Resource
    Low-density dislocation arrays at heteroepitaxial Ge/GaAs-interfaces investigated by high voltage electron microscopy (1979)
    Springer
    Applied physics 18 (1979), S. 67-75 
    Details
    ISSN: 1432-0630
    Keywords: 68.55 ; 61.70
    Source: Springer Online Journal Archives 1860-2000
    Topics: Mechanical Engineering, Materials Science, Production Engineering, Mining and Metallurgy, Traffic Engineering, Precision Mechanics , Physics
    Notes: Abstract High-voltage electron microscopy in combination with a large-area thinning technique has been applied to thin epitaxial Ge layers on GaAs substrates. These layers exhibit 60° misfit dislocations along the 〈110〉 directions parallel to the interface. Various dislocation reactions are evaluated from the electron micrographs, e.g. the formation of non-glissile 90° dislocations from two nearly parallel 60° dislocations and the annihilation reaction of two crossing 60° dislocations with identical Burgers vectors. The latter reaction occasionally leads to a dislocation multiplication. The misfit dislocations in very thin layers (∼0.5 μm thickness and a linear dislocation density of less than 100 dislocation lines/cm) tend to be arranged in groups rather than being equidistant. Consequences for the interpretation of x-ray topograms are discussed.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00935905
    Library Location Call Number Volume/Issue/Year Availability
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    Paper (German National Licenses)
    Fulltext
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