ISSN:
1089-7550
Source:
AIP Digital Archive
Topics:
Physics
Notes:
We have investigated the thermal stability of n+ polycrystalline-Si(poly-Si)/ZrO2(50–140 Å)/SiO2(7 Å)/p-Si metal–oxide–semiconductor (MOS) capacitors via electrical and material characterization. The ZrO2 gate dielectric was prepared by atomic layer chemical vapor deposition using ZrCl4 and H2O vapor. Capacitance–voltage hysteresis as small as ∼12 mV with the flatband voltage of −0.5 V and the interface trap density of ∼5×1010 cm−2 eV−1 were attained with activation anneal at 750 °C. A high level of gate leakage current was observed at the activation temperatures over 750 °C and attributed to the interfacial reaction of poly-Si and ZrO2 during the poly-Si deposition and the following high temperature anneal. Because of this, the ZrO2 gate dielectric is incompatible with the conventional poly-Si gate process. In the MOS capacitors having a smaller active area (〈50×50 μm2), fortunately, the electrical degradation by further severe silicidation does not occur up to an 800 °C anneal in N2 for 30 min. © 2002 American Institute of Physics.
Type of Medium:
Electronic Resource
URL:
http://dx.doi.org/10.1063/1.1425073
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