ISSN:
1089-7550
Source:
AIP Digital Archive
Topics:
Physics
Notes:
In in-plane-gate transistors, gate, drain, and source are lying in one plane, leading to a very efficient lateral electric field effect. This concept proved to be reliable and such transistors have been realized on a number of different semiconductor material systems. Here, we present focused ion-beam implanted in-plane-gate transistors on standard bulk silicon and some attempts to understand their physics, possibly opening the way to significantly reduce their dimensions from what is now, typically, 1–3 μm into the quantum regime. The transistors are written using a 100 keV gallium ion beam with a focus of 100 nm into a thin arsenic doped n-type layer on a prestructured standard 3 in. p-type (100) silicon wafer and subsequent rapid thermal annealing. The devices are characterized electrically by direct current measurements at room temperature. They show very promising features, for example, a drain saturation current of 35 μA combined with a relatively high differential output resistance of 900 kΩ and a transconductance of up to 29 μS, which is much higher than the value recently obtained on separation-by-implantation-of-oxygen substrates. The voltage dependent spreading of the depletion zones shows a square-root law. The drain current of the devices depends strongly on the substrate bias. It is shown that this is due to a biasing of the lateral gate lines via the substrate, caused by the vertical geometry of the transistors. © 1997 American Institute of Physics.
Type of Medium:
Electronic Resource
URL:
http://dx.doi.org/10.1063/1.366199
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