ISSN:
0954-0911
Source:
Emerald Fulltext Archive Database 1994-2005
Topics:
Mechanical Engineering, Materials Science, Production Engineering, Mining and Metallurgy, Traffic Engineering, Precision Mechanics
Notes:
A new concept of 3D-electronic packaging is presented: Si-on-Si multi-chip module flip-chip technology with arrays of fine etched and filled vertical electrical interconnections (vias). Arrays of vias with a high number of interconnections, and not only peripheral interconnections are used. A 3D Si-on-Si stack package demonstrator has been realized consisting of four Si-substrates each representing a system level and containing four thinned and flip-chip assembled chips. The chips are flip-chip mounted on the flat side of the Si-substrates. When interconnecting the Si-substrates by bump technology the chips submerge into cavities on the rear side of the adjacent Si-substrate. The chips also test the technology and quality of the electronic packaging, and therefore contain a set of thin film heaters, junctions for temperature measuring, Al-meanders for stress and strain measuring and daisy chains for conduction path monitoring.
Type of Medium:
Electronic Resource
URL:
http://dx.doi.org/10.1108/09540910010312429
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