ISSN:
1573-1979
Keywords:
delay lines
;
time-to-digital converters
;
high speed circuits
Source:
Springer Online Journal Archives 1860-2000
Topics:
Electrical Engineering, Measurement and Control Technology
Notes:
Abstract Delay-controlled CMOS delay lines have been proved useful in a number of applications, notably the digitization of short time intervals. This paper introduces a new kind of CMOS delay line, in which the delay element is an array of capacitors controlled by a digital signal vector. This choice allows for a robust implementation of the circuitry controlling the delay generation, while the maximum speed attainable by the line is high compared to the maximum speed achieved by other delay line architectures. The delay line presented here was designed to produce an accurately tunable 16 × 0.5ns delay under large temperature, supply voltage, and technological process quality variations.
Type of Medium:
Electronic Resource
URL:
http://dx.doi.org/10.1023/A:1008359721539
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