ISSN:
1089-7623
Source:
AIP Digital Archive
Topics:
Physics
,
Electrical Engineering, Measurement and Control Technology
Notes:
Utilizing the propagation delay in a chain of logic elements to digitize short time intervals has a high potential in various applications because the method has an ultrashort measurement "dead time" and its complete timing circuit can be easily integrated in a single semiconductor chip. However, the existing single-lined chain suffers from serious nonlinearity due to the longer path lengths at the foldings which are unavoidable when the number of delay elements is large as high time resolution requires. We propose a new configuration in which the delay chain is branched. The delay elements of each branch evenly subdivide the corresponding larger folding path so all units have the same delay time. The proposed time-to-digital converter with an 81-delay-unit branched chain and a built-in calibration circuit has been implemented on a commercial programmable logic device. It is used to interpolate different time durations within the 100 ns period of a standard 10 MHz clock. The digital time deviates less than 0.3 ns throughout the entire range. A similar single-lined delay chain, constructed for comparison, exhibits timing error up to 32.7 ns. A major improvement in linearity has been achieved by our device. © 2000 American Institute of Physics.
Type of Medium:
Electronic Resource
URL:
http://dx.doi.org/10.1063/1.1150650
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