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  • 1
    Electronic Resource
    Electronic Resource
    Partitioning Processor Arrays under Resource Constraints (1997)
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 17 (1997), S. 5-20 
    Details
    ISSN: 1573-109X
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract A single integer linear programming model for optimally scheduling partitioned regular algorithms is presented. The herein presented methodology differs from existing methods in the following capabilities: 1) Not only constraints on the number of available processors and communication capabilities are taken into account, but also local memories and constraints on the size of available memories. 2) Different types of processors can be handled. 3) The size of the optimization model (number of integer variables) is independent of the size of the tiles to be executed. Hence, 4) the number of integer variables in the optimization model is greatly reduced such that problems of relevant size can be solved in practical execution time.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1007935215591
    Library Location Call Number Volume/Issue/Year Availability
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    Paper (German National Licenses)
    Fulltext
  • 2
    Electronic Resource
    Electronic Resource
    Multidimensional Exploration of Software Implementations for DSP Algorithms (2000)
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 24 (2000), S. 83-98 
    Details
    ISSN: 1573-109X
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract When implementing software for programmable digital signal processors (PDSPs), the design space is defined by a complex range of constraints and optimization objectives. Three implementation metrics that are crucial in many PDSP applications are the program memory requirement (code size), data memory requirement, and execution time. This paper addresses the problem of exploring the 3-dimensional space of trade-offs that is defined by these crucial metrics. Given a software library for a target PDSP, and a dataflow-based block diagram specification of a DSP application in terms of this library, our objective in this paper is to compute a full range of Pareto-optimal solutions. For solving this multi-objective optimization problem, an evolutionary algorithm based approach is applied. We illustrate our techniques by analyzing the trade-off fronts of a practical application for a number of well-known, commercial PDSPs.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008170728742
    Library Location Call Number Volume/Issue/Year Availability
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    Paper (German National Licenses)
    Fulltext
  • 3
    Electronic Resource
    Electronic Resource
    Control generation in the design of processor arrays (1991)
    Springer
    The journal of VLSI signal processing systems for signal, image, and video technology 3 (1991), S. 77-92 
    Details
    ISSN: 1573-109X
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract The problem of mapping algorithms onto regular arrays has received great attention in the past. Results are available on the mapping of regular algorithms onto systolic or wavefront arrays. On the other hand, many algorithms that can be implemented on parallel architectures are not completely regular but are composed of a set of regular subalgorithms. Recently, a class of configurable processor arrays has been proposed that allows the efficient implementation of piecewise regular algorithms. In contrary to pure systolic of wavefront arrays they are distinguished by a dynamic configuration structure. The known trajectories, however, cannot be applied to the design of configurable processor arrays because the functions of the procesing elements and the interconnection structure are time- and space-dependent. In this paper, a systematic procedure is introduced that allows the efficient design of configurable processor arrays including the specification of the processing elements and the generation of control signals. Control signals are propagated through the processor array. The proposed design trajectory can be used for the design of regular arrays or configurable arrays.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF00927836
    Library Location Call Number Volume/Issue/Year Availability
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    Paper (German National Licenses)
    Fulltext
  • 4
    Electronic Resource
    Electronic Resource
    System-Level Synthesis Using Evolutionary Algorithms (1998)
    Springer
    Design automation for embedded systems 3 (1998), S. 23-58 
    Details
    ISSN: 1572-8080
    Keywords: System-synthesis ; hardware/software partitioning ; design space exploration ; evolutionary algorithms
    Source: Springer Online Journal Archives 1860-2000
    Topics: Computer Science
    Notes: Abstract In this paper, we consider system-level synthesis as the problem of optimally mapping a task-level specification onto a heterogeneous hardware/software architecture. This problem requires (1) the selection of the architecture (allocation) including general purpose and dedicated processors, ASICs, busses and memories, (2) the mapping of the specification onto the selected architecture in space (binding) and time (scheduling), and (3) the design space exploration with the goal to find a set of implementations that satisfy a number of constraints on cost and performance. Existing methodologies often consider a fixed architecture, perform the binding only, do not reflect the tight interdependency between binding and scheduling, do not consider communication (tasks and resources), or require long run-times preventing design space exploration, or yield only one implementation with optimal cost. Here, a model is introduced that handles all mentioned requirements and allows the task of system-synthesis to be specified as an optimization problem. The application and adaptation of an Evolutionary Algorithm to solve the tasks of optimization and design space exploration is described.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1023/A:1008899229802
    Library Location Call Number Volume/Issue/Year Availability
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    Paper (German National Licenses)
    Fulltext
  • 5
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    HighPerMeshes - A Domain-Specific Language for Numerical Algorithms on Unstructured Grids (2021)
    Details
    Publication Date: 2022-12-12
    Description: Solving partial differential equations on unstructured grids is a cornerstone of engineering and scientific computing. Nowadays, heterogeneous parallel platforms with CPUs, GPUs, and FPGAs enable energy-efficient and computationally demanding simulations. We developed the HighPerMeshes C++-embedded Domain-Specific Language (DSL) for bridging the abstraction gap between the mathematical and algorithmic formulation of mesh-based algorithms for PDE problems on the one hand and an increasing number of heterogeneous platforms with their different parallel programming and runtime models on the other hand. Thus, the HighPerMeshes DSL aims at higher productivity in the code development process for multiple target platforms. We introduce the concepts as well as the basic structure of the HighPer-Meshes DSL, and demonstrate its usage with three examples, a Poisson and monodomain problem, respectively, solved by the continuous finite element method, and the discontinuous Galerkin method for Maxwell’s equation. The mapping of the abstract algorithmic description onto parallel hardware, including distributed memory compute clusters is presented. Finally, the achievable performance and scalability are demonstrated for a typical example problem on a multi-core CPU cluster.
    Language: English
    Type: article , doc-type:article
    Library Location Call Number Volume/Issue/Year Availability
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