ISSN:
1573-0727
Schlagwort(e):
high-level test generation
;
assertion test generation
;
design validation
;
logic verification
;
symbolic trajectory evaluation
Quelle:
Springer Online Journal Archives 1860-2000
Thema:
Elektrotechnik, Elektronik, Nachrichtentechnik
Notizen:
Abstract Test and validation of embedded array blocks remains a major challenge in today's microprocessor design environment. The difficulty comes from twofold, the sizes of the arrays and the complexity of their timing and control. This paper describes a novel test generation methodology for test and validation of microprocessor embedded arrays. Unlike traditional ATPG methods, our test generation method is based upon the high-level assertion specification which is originally used for the purpose of formal verification. The superiority of these assertion tests over the traditional ATPG tests will be discussed and shown through various experiments on recent PowerPC microprocessor designs.
Materialart:
Digitale Medien
URL:
http://dx.doi.org/10.1023/A:1008353704141
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