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The PAPIA system

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Abstract

In 1983 an Italian research program was begun for the design, simulation and construction of a multiprocessor image processing system. After a first phase devoted to the comparison of suggested and existing systems and to the definition of a set of benchmarks, a new system was defined. The structure of this new system is introduced here: it is based on a fine-grained pyramid of processors built up by means of a pyramidal cell implemented on a VLSI multiprocessor chip. The peculiarities and the capabilities of the processing element are highlighted. The complete hardware and software system has been fully designed and is described. A first working prototype has been built and is now operational.

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Authors and Affiliations

  1. Dipartimento di Informatica e Sistemistica, Università di Pavia, Pavia, Italy

    V. Cantoni & M. Ferretti

  2. Dipartimento di Matematica ed Applicazioni, Università di Palermo, Palermo, Italy

    V. Di Gesu

  3. IFCAI-CNR, Palermo

    V. Di Gesu

  4. Dipartimento di Matematica, Università La Sapienza, Roma, Italy

    S. Levialdi

  5. Dipartimento di Elettronica, Politecnico di Milano, Milano, Italy

    R. Negrini & R. Stefanelli

Authors
  1. V. Cantoni
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  2. V. Di Gesu
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  3. M. Ferretti
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  4. S. Levialdi
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  5. R. Negrini
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  6. R. Stefanelli
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Cantoni, V., Di Gesu, V., Ferretti, M. et al. The PAPIA system. J VLSI Sign Process Syst Sign Image Video Technol 2, 195–217 (1991). https://doi.org/10.1007/BF00925466

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  • DOI: https://doi.org/10.1007/BF00925466

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