Skip to main content
SpringerLink
Log in

Process integration technologies for sub-half micron BiCMOS LSls

Technologien der Prozeßintegration für Sub-half Micron BiCMOS LSls

  • Published:
Electrical Engineering Aims and scope Submit manuscript

Contents

The process integration issues and various approches to reduce process steps for high performance/low cost sub-half micron BiCMOS LSIs are reviewed. Using these technologies, the bipolar transistor process is added with minimum increase in process complexity, while maintaining compatiblity with a state-of-the-art CMOS process. Future prospects for high performance BiCMOS device/process technologies are addressed.

Übersicht

Aspekte der Prozeßintegration sowie verschiedene Ansätze zur Reduzierung der Prozeßschritte für hochleistungsfähige und preisgünstige sub-half micron BiCMOS LSIs werden in diesem Aufsatz diskutiert. Die Anwendung der zu beschreibenden Technologien ermöglicht das Hinzufügen des Bipolartransistor-Prozesses bei einem nur minimalen Anstieg der Prozeßkomplexität und Erhalt der Kompatibilität zur gegenwärtigen CMOS-Technologie. Abschließend werden

Zukunftsperspektiven der BiCMOS-Technologie erörtert.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. Yamazaki, T.; Suzuki, H.; Yoshida, H.; Nakamura, K.; Kuhara, S.; Kimura, T.; Takada, M.: A High Performance 0.4 μm BiCMOS Technology for 16 Mb Fast SRAMs. Proceedings of ESSDERC (1994) 191–194

  2. Okamura, H.; Toyoshima, H.; Takeda, K.; Oguri, T.; Nakamura, S.; Takada, M.; Imai, K.; Kinoshita, Y.; Yoshida, H.; Yamazaki, T.: A 1ns 1W, 2.5V, 32Kb NTL-CMOS SRAM Macro Using a Memory Cell with P-Channel Access Transistors. ISSCC Dig. Tech. Paper (1995) 306–307

  3. Okamoto, F.; Hagihara, Y.; Ohkubo, C.; Sekine, Y.; Nishi, N.; Yamada, H.; Enomoto, T.: A 200MFLOPS 100 Mhz 64b BiCMOS Vector-pipelined-processor. ISSCC Dig. Tech. Paper (1991) 256–257

  4. Sone, K.;Nishida, Y.;Nakadai, N.: A 10b 100Msample/s pipelined subranging BiCMOS ADC. IEEE J. Solid-State Circuits 28 (1993) 1180–1186

    Google Scholar 

  5. Kinoshita, Y.; Imai, K.; Yoshida, H.; Suzuki, H.; Tatsumi, T.; Yamazaki, T.: Process Integration Technology for sub-30ps ECL BiCMOS using heavily Boron Doped Epitaxial Contact (HYDEC). IEDM Tech. Dig. (1994) 441–444

  6. Soejima, K.; Shida, A.; Hirata, M.; Koga, H.; Ukai, J.; Sata, H.: A BiCMOS Technology with 660 Mhz Vertical PNP Transistor for Analog/digital ASICs. Proceedings of IEEE Custom Integrated Circuits Conference (1989) 18.6.1–18.6.4

  7. Yoshida, H.;Suzuki, H.;Kinoshita, Y.;Imai, K.;Akimoto, T.;Tokashiki, K.: Process Integration Technology for Low Process Complexity BiCMOS using Trench Collector Sink. NEC Research and Development 36 (1995) 376–382

    Google Scholar 

  8. Yoshida, H.; Suzuki, H.; Kinoshita, Y.; Imai, K.; Akimoto, T.; Tokashiki, K.; Madihian, M.; Yamazaki, T.: A Premetal BPSG Filled Deep Trench Isolation Technology for ECL-BiCMOS LSIs using CMP. Proceeding of ESSDERC (1995) 367–370

  9. Yamashina, M.;Goto, J.;Okamoto, F.;Ando, K.;Yamada, H.;Horiuchi, T.;Nakamura, K.;Enomoto, T.: A 200-Mhz 16-bit Super High-Speed Signal Processor (SSSP) LSI. IEEE J. Solid-State Circuits 24 (1989) 1668–1674

    Google Scholar 

  10. Tago, S.; Matsumoto, N.; Kaga, H.; Ogawa, T.; Ohkawa, S.; Kobayshi, M.: A sub-50psec, 89Kgate ECL-Gate Array with 480Kb BiCMOS STRAM. Proceedings of IEEE ASIC Conference (1993) 174–177

  11. Madihian, M.; Bak, E.; Imai, K.; Yoshida, H.; Kinoshita, Y.; Yamazaki, T.: A 2V BiCMOS Receiver Chip for L-S-C Band Personal Networks. VLSI Circuits Symp. Dig. Tech. Papers (1995) 89–90

  12. Huang, W. L. M.;Klein, K. M.;Grimaldi, M.;Racanelli, M.;Ramaswami, S.;Tsao, J.;Foerstner, J.;Hwang, B. Y. C.: TFSOI Complementary BiCMOS Technology for Low Power Applications. IEEE Trans. Electron Devices 42 (1995) 506–512

    Google Scholar 

  13. Nguyen-Ngoc, D.; Harame, D. L.; Malinowski, J. C.; Jeng, S. J.: Schnonenberg, K. T.; Gilbert, M. M.; Berg, G. D.; Wu, S.; Soyuer, M.; Tallman, K. A.; Stein, K. J.; Groves, R. A.; Subbanna, S.; Colavito, D. B.; Sunderland, D. A.; Meyerson, B. S.: A 200 mm SiGe-HBT BiCMOS Technology for Mixed Signal Application. Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting (1995) 89–92

Download references

Author information

Authors and Affiliations

  1. Logic Device Development Laboratory ULSI Device Development Laboratorties, NEC Corporation, 1120, Shimokuzawa, Sagamihara, 229, Kanagawa, Japan

    T. Yamazaki, K. Imai, H. Yoshida, Y. Kinoshita & H. Suzuki

Authors
  1. T. Yamazaki
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. K. Imai
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. H. Yoshida
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Y. Kinoshita
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. H. Suzuki
    View author publications

    You can also search for this author in PubMed Google Scholar

Additional information

The authors would like to thank Drs. M. Kamoshida, K. Okada and M. Nakamae for their encouragement throughout this work.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Yamazaki, T., Imai, K., Yoshida, H. et al. Process integration technologies for sub-half micron BiCMOS LSls. Electrical Engineering 79, 329–333 (1996). https://doi.org/10.1007/BF01235873

Download citation

  • Received:

  • Issue Date:

  • DOI: https://doi.org/10.1007/BF01235873

Keywords

Search

Navigation