Low noise-low power monolithic multiplexing readout electronics for silicon strip detectors

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Abstract

A 128 channel readout chip suitable for readout with 50 μm pitch has been developed in CMOS technology. It provides signal amplification, parallel data storage and serial readout. Switched capacitor technique is used for noise reduction by multicorrelated sampling and simultaneously for second stage amplification. Power consumption is controlled by an externally applied reference voltage thereby allowing for an optimization of speed and noise versus power consumption for the individual needs of the particular experiment. Pulsed mode operation for further reduction of heat dissipation is easily possible without cutting the supply voltages. Very good noise performance (250+45CD[pF] electrons) low input impedance (Ceff > 200 pF) and large amplification (70 mV/fC) have been obtained at very low power consumption (1.6 mW per channel). The chip may be used for both synchronous (e.g. collider) and asynchronous (fixed target) applications where the time of the event is not known in advance. A second version with only 64 channels suitable for 100 μm pitch is in preparation. Further developments presently under way include the introduction of combinded CMOS-JFET technology.

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