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Residue systolic implementations for neural networks

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Abstract

In this work we propose two techniques for improving VLSI implementations for artificial neural networks (ANNs). By making use of two kinds of processing elements (PEs), one dedicated to the basic operations (addition and multiplication) and another to evaluate the activation function, the total time and cost for the VLSI array implementation of ANNs can be decreased by a factor of two compared with previous work. Taking the advantage of residue number system, the efficiency of each PE can be further increased. Two RNS- based array processor designs are proposed. The first is built by look-up tables, and the second is constructed by binary adders accomplished by the mixed- radix conversion (MRC), such that the hardwares are simple and high speed operations are obtained. The proposed techniques are general enough to be extended to cover other forms of loading and learning algorithms.

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Author notes

  1. C. N. Zhang

    Present address: Department of Computer Science, University of Regina, Saskatchewan, Canada

Authors and Affiliations

  1. Department of Computer Science, University of Regina, Saskatchewan, Canada

    M. Wang

  2. Department of Computer Science & Information Engineering, National Chiao-Tung University, Taiwan, ROC

    C. C. Tseng

Authors
  1. C. N. Zhang
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  2. M. Wang
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  3. C. C. Tseng
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Zhang, C.N., Wang, M. & Tseng, C.C. Residue systolic implementations for neural networks. Neural Comput & Applic 3, 149–156 (1995). https://doi.org/10.1007/BF01414076

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  • DOI: https://doi.org/10.1007/BF01414076

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