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Closed‐loop control of switched reluctance generators

E.P. Kennedy (School of Electronic Engineering, Dublin City University, Dublin, Ireland)
A.J. Murphy (School of Electronic Engineering, Dublin City University, Dublin, Ireland)
M. Condon (School of Electronic Engineering, Dublin City University, Dublin, Ireland)
J. Dowling (School of Electronic Engineering, Dublin City University, Dublin, Ireland)

Abstract

Purpose

This paper deals with closed‐loop control of a switched reluctance generator (SRG).

Design/methodology/approach

The control objective when generating is to maintain the dc link voltage at the required value while achieving maximum efficiency. Three possible control schemes are presented and their performance is examined by testing on an experimental 12/8 three‐phase SRG.

Findings

A very simple control scheme that requires no prior characterisation of the SRG, an approach based on the use of an inverse machine model and finally, a control scheme that is aimed at achieving optimal efficiency are described and experimental results for all three are presented.

Research limitations/implications

The inverse machine model control scheme and the optimal efficiency control scheme require operation at a constant voltage reference for accurate operation (although this is the case for many generator applications). Possible future research might include the expansion of these control schemes to operation with a variable voltage reference.

Practical implications

The importance of maximising efficiency is emphasised with a clear method of deriving the optimal efficiency firing angles described.

Originality/value

This paper provides a good overview of SRG operation through the experimental implementation of three separate closed‐loop voltage control schemes, each of which is described in detail.

Keywords

Citation

Kennedy, E.P., Murphy, A.J., Condon, M. and Dowling, J. (2005), "Closed‐loop control of switched reluctance generators", COMPEL - The international journal for computation and mathematics in electrical and electronic engineering, Vol. 24 No. 2, pp. 662-681. https://doi.org/10.1108/03321640510571156

Publisher

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Emerald Group Publishing Limited

Copyright © 2005, Emerald Group Publishing Limited

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