Fully scalable gain memory cell for future drams

https://doi.org/10.1016/0167-9317(91)90246-AGet rights and content

Abstract

A dynamic memory cell is described in which charge is stored on the gate capacitance of a MOS transistor rather than on a discrete capacitor. This transistor is used as an amplifying device, so that the output charge is much greater than the charge stored in the cell. The memory cell can be scaled down without performance loss.

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