A 66 MHz, 32-channel analog memory circuit with data selection for fast silicon detectors

doi:10.1016/0168-9002(93)90339-J

Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment

Volume 326, Issues 1–2, 1 March 1993, Pages 100-111

https://doi.org/10.1016/0168-9002(93)90339-J Get rights and content

Abstract

An analog memory array with 64 memory cells for each channel has been designed and manufactured in CMOS. A new skip logic controller allows to write at 66 MHz without dead time and to read out at a lower frequency simultaneously. The input circuit is charge-sensitive and integrates continuously. Pedestal nonuniformity is 1.4 mV rms from cell-to-cell and 3.5 mV rms between channels. The linearity range is −2.5 to +1.5 V, which corresponds to 11 bits. The chip has been used in a particle detection test.

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Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment

A 66 MHz, 32-channel analog memory circuit with data selection for fast silicon detectors

Abstract

Nucl. Instr. and Meth.

CERN report CERN 89-10

CERN report CERN 9010

CERN report CERN 9010

Design study of a low-power, low-noise front-end for multianode silicon drift detectors

Smart readout of silicon drift detector using ON-LINE fuzzy logic

Switched capacitor arrays analog memory for sparse data sampling

Silicon drift detector readout and on-line data reduction using a fast VLSI dedicated fuzzy processor

Software engineering techniques and CASE tools in RD13

DYN1: a 66 MHz front end analog memory chip with first level trigger capture for use in future high luminosity particle physics experiments