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  • integrate-and-fire models  (1)
  • neuromorphic  (1)
  • neuromorphic analog VLSI  (1)
  • 1
    Electronic Resource
    Electronic Resource
    Springer
    Journal of computational neuroscience 2 (1995), S. 63-82 
    ISSN: 1573-6873
    Keywords: voltage threshold ; current threshold ; action potential initiation ; integrate-and-fire models ; single cell models
    Source: Springer Online Journal Archives 1860-2000
    Topics: Computer Science , Medicine , Physics
    Notes: Abstract The majority of neural network models consider the output of single neurons to be a continuous, positive, and saturating firing ratef(t), while a minority treat neuronal output as a series of delta pulses ∑δ (t — t i ). We here argue that the issue of the proper output representation relates to the biophysics of the cells in question and, in particular, to whether initiation of somatic action potentials occurs when a certain thresholdvoltage or a thresholdcurrent is exceeded. We approach this issue using numerical simulations of the electrical behavior of a layer 5 pyramidal cell from cat visual cortex. The dendritic tree is passive while the cell body includes eight voltage- and calcium-dependent membrane conductances. We compute both the steady-state (I ∞ static (V m )) and the instantaneous (I o (Vm)) I–V relationships and argue that the amplitude of the local maximum inI ∞ static (V m ) corresponds to the current thresholdI th for sustained inputs, while the location of the middle zero-crossing ofI o corresponds to a fixed voltage thresholdV th for rapid inputs. We confirm this using numerical simulations: for “rapid” synaptic inputs, spikes are initiated if the somatic potential exceedsV th, while for slowly varying inputI th must be exceeded. Due to the presence of the large dendritic tree, no charge thresholdQ th exists for physiological input. Introducing the temporal average of the somatic membrane potential 〈(V m)〉 while the cell is spiking repetitively, allows us to define a dynamic I-V relationship ∞ dynamic (〈(V m)〉). We find an exponential relationship between 〈(V m)〉 and the net current sunk by the somatic membrane during spiking (diode-like behavior). The slope ofI∞/dynamic(〈(V m))〉 allows us to define a dynamic input conductance and a time constant that characterizes how rapidly the cell changes its output firing frequency in response to a change in its input.
    Type of Medium: Electronic Resource
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  • 2
    Electronic Resource
    Electronic Resource
    Springer
    Analog integrated circuits and signal processing 13 (1997), S. 69-78 
    ISSN: 1573-1979
    Keywords: neuromorphic analog VLSI ; saccadic eye movements ; learning ; floating-gate ; short-term adaptation
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract In this paper we describe an analog VLSI circuit, fabricatedusing a standard 2 µm, n-well, BiCMOS process,which utilizes floating-gate structures for non-volatile, on-chip,analog parameter storage. This circuit is designed to operatein the context of a hardware model of the primate oculomotorsystem and performs visually-guided, saccadic adaptation. Thechip contains a one-dimensional array of photoreceptors and floating-gatecircuits which are used to map retinal positions to motor outputcommands. The system's functionality is demonstrated by trainingthe chip with several different mapping functions using a supervised-learningtechnique.
    Type of Medium: Electronic Resource
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  • 3
    Electronic Resource
    Electronic Resource
    Springer
    Analog integrated circuits and signal processing 24 (2000), S. 195-211 
    ISSN: 1573-1979
    Keywords: analog VLSI ; vision chips ; optical flow ; stereo ; neuromorphic
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract The extent of pixel-parallel focal plane image processing is limited by pixel area and imager fill factor. In this paper, we describe a novel multi-chip neuromorphic VLSI visual motion processing system which combines analog circuitry with an asynchronous digital interchip communications protocol to allow more complex pixel-parallel motion processing than is possible in the focal plane. This multi-chip system retains the primary advantages of focal plane neuromorphic image processors: low-power consumption, continuous-time operation, and small size. The two basic VLSI building blocks are a photosensitive sender chip which incorporates a 2D imager array and transmits the position of moving spatial edges, and a receiver chip which computes a 2D optical flow vector field from the edge information. The elementary two-chip motion processing system consisting of a single sender and receiver is first characterized. Subsequently, two three-chip motion processing systems are described. The first three-chip system uses two sender chips to compute the presence of motion only at a particular stereoscopic depth from the imagers. The second three-chip system uses two receivers to simultaneously compute a linear and polar topographic mapping of the image plane, resulting in information about image translation, rotation, and expansion. These three-chip systems demonstrate the modularity and flexibility of the multi-chip neuromorphic approach.
    Type of Medium: Electronic Resource
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