ISSN:
1573-1979
Keywords:
interconnect
;
CMOS inverter model
;
interconnect delay
;
power dissipation
;
short-circuit power
Source:
Springer Online Journal Archives 1860-2000
Topics:
Electrical Engineering, Measurement and Control Technology
Notes:
Abstract A delay and power model of a CMOS inverter driving aresistive-capacitive load is presented. The model is derivedfrom Sakurai‘s alpha-power law and exhibits good accuracy. Themodel can be used to design and analyze those CMOS invertersthat drive a large RC load when considering bothspeed and power. Expressions are provided for estimating thepropagation delay and transition time which exhibit less than27% discrepancy from SPICE for a wide variety of RCloads. Expressions are also provided for modeling the short-circuitpower dissipation of a CMOS inverter driving a resistive-capacitiveinterconnect line which are accurate to within 15% of SPICEfor most practical loads.
Type of Medium:
Electronic Resource
URL:
http://dx.doi.org/10.1023/A:1008282308028
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