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  • 1
    Electronic Resource
    Electronic Resource
    Reverse-bias current reduction in low-temperature-annealed silicon pn junctions by ultraclean ion-implantation technology (1990)
    [S.l.] : American Institute of Physics (AIP)
    Journal of Applied Physics 67 (1990), S. 7404-7412 
    Details
    ISSN: 1089-7550
    Source: AIP Digital Archive
    Topics: Physics
    Notes: Reduction in the reverse-bias current in low-temperature-annealed silicon pn junctions has been studied. It has been shown that the transition region existing underneath the ion-implantation-generated amorphous layer and the contamination incorporated into this region play a decisive role in determining the reverse current level. In order to minimize the contamination involvement into the transition region, ultraclean ion-implantation technology has been developed. Ion implantation was carried out under a UHV (5×10−10 Torr) condition in order to minimize the recoil implantation of adsorbed contamination at the surface. The contamination due to the high-energy ion-beam sputtering of component parts in the ion implanter has also been suppressed. As a result, a low reverse-bias current level of about 1.2×10−7 A/cm2 has been obtained for arsenic-implanted n+p junctions annealed at 550 °C, which is more than two orders of magnitude smaller than that previously reported. The stress compensation technology employing combined implantation of phosphorus and arsenic has also been shown to be very effective in reducing the lattice strain and in suppressing the damage generation.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1063/1.344529
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    Paper (German National Licenses)
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  • 2
    Electronic Resource
    Electronic Resource
    Formation of low reverse current ion-implanted n+p junctions by low-temperature annealing (1989)
    Woodbury, NY : American Institute of Physics (AIP)
    Applied Physics Letters 55 (1989), S. 966-968 
    Details
    ISSN: 1077-3118
    Source: AIP Digital Archive
    Topics: Physics
    Notes: By employing stress compensation technology in conjunction with an ultrahigh vacuum ion implanter, we have obtained two orders of magnitude smaller reverse-bias current levels in n+p junctions annealed at 550 °C as compared to the previous data. When samples are made with an optimum stress compensation condition, the magnitude of reverse-bias currents in n+p junctions as well as the carrier deactivation during post-implantation anneal becomes smallest. In order to further reduce the reverse-bias current level, it is shown that the elimination of contamination involvement during the implantation process is most essential.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1063/1.101691
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    Paper (German National Licenses)
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