Electronic Resource
Woodbury, NY
:
American Institute of Physics (AIP)
Applied Physics Letters
71 (1997), S. 719-721
ISSN:
1077-3118
Source:
AIP Digital Archive
Topics:
Physics
Notes:
This has been accomplished in the past using four/five separate electrode- and diffusion-barrier layers. In this letter, we report a novel Pt–Rh–Ox/Pt–Rh/Pt–Rh–Ox electrode-barrier structure which acts as an electrode as well as a diffusion barrier for integration of the ferroelectric capacitors directly onto silicon deposited using an in situ reactive rf sputtering process. The electrodes have a smooth and fine grained microstructure and are excellent diffusion barriers between the PbZr0.53Ti0.47O3 (PZT) and Si substrate and exhibit good thermal stability up to very high processing temperatures of 700 °C. The ferroelectric (PZT) test capacitors using these electrode barriers grown directly on Si, show well saturated hysteresis loops with Pr and Ec of 16 μC/cm2 and 30–40 kV/cm, respectively. The capacitors exhibit no significant fatigue loss (〈5%) up to 1011 cycles and have low leakage currents (2×10−8 A/cm2 at 100 kV/cm). These electrode barriers can be used to directly integrate the thin film capacitors on the source/drain of the transistors of the memory cell structure for accomplishing large scale integration.© 1997 American Institute of Physics.
Type of Medium:
Electronic Resource
URL:
http://dx.doi.org/10.1063/1.119840
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