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  • 1
    Electronic Resource
    Electronic Resource
    Springer
    Formal methods in system design 11 (1997), S. 5-21 
    ISSN: 1572-8102
    Keywords: Decision Diagrams (DDs) ; OKFDDs ; OBDDs ; OFDDs ; decomposition types ; exponential gaps
    Source: Springer Online Journal Archives 1860-2000
    Topics: Computer Science
    Notes: Abstract Ordered Decision Diagrams (ODDs) as a means for the representation of Boolean functions are used in many applications in CAD. Depending on the decomposition type, various classes of ODDs have been defined, among them being the Ordered Binary Decision Diagrams (OBDDs), the Ordered Functional Decision Diagrams (OFDDs) and the Ordered Kronecker Functional Decision Diagrams (OKFDDs). Based on a formalization of the concept decomposition type we first investigate all possible decomposition types and prove that already OKFDDs, which result from the application of only three decomposition types, result in the most general class of ODDs. We then show from a (more) theoretical point of view that the generality of OKFDDs is really needed. We prove several exponential gaps between specific classes of ODDs, e.g. between OKFDDs on the one side and OBDDs, OFDDs on the other side. Combining these results it follows that a restriction of the OKFDD concept to subclasses, such as OBDDs and OFDDs as well, results in families of functions which lose their efficient representation.
    Type of Medium: Electronic Resource
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  • 2
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 14 (1999), S. 219-225 
    ISSN: 1573-0727
    Keywords: AND/EXOR ; 2-level circuits ; random pattern testability ; synthesis for testability
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract It is often stated that AND/EXOR circuits are much easier to test than AND/OR circuits. This statement, however, only holds true for circuits derived from restricted classes of AND/EXOR expressions, like positive polarity Reed-Muller and fixed polarity Reed-Muller expressions. For these two classes of expressions, circuits with good deterministic testability properties are known. In this paper we show that these circuits also have good random pattern testability attributes. An input probability distribution is given that yields a short expected test length for biased random patterns. This is the first time theoretical results on random pattern testability are presented for 2-level AND/EXOR circuit realizations of arbitrary Boolean functions. It turns out that analogous results cannot be expected for less restricted classes of 2-level AND/EXOR circuits. We present experiments demonstrating that generally minimized 2-level AND/OR circuits can be tested as easy (or hard) as minimized 2-level AND/EXOR circuits.
    Type of Medium: Electronic Resource
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  • 3
    Electronic Resource
    Electronic Resource
    Springer
    Journal of electronic testing 7 (1995), S. 173-191 
    ISSN: 1573-0727
    Keywords: design for testability ; path delay fault model ; testability preserving transformations ; testability inproving transformations
    Source: Springer Online Journal Archives 1860-2000
    Topics: Electrical Engineering, Measurement and Control Technology
    Notes: Abstract Several synthesis for path delay fault (PDF) testability approaches are based on local transformations of digital circuits. Different methods were used to show that transformations preserve or improve PDF testability. In this paper we present a new unifying approach to show that local transformations preserve or improve PDF testability. This approach can be applied to every local transformation and in contrast to previously published methods only the subcircuits to be transformed have to be considered. Using our new approach we are able to show in a very convenient way that the transformations which are already used in synthesis tools preserve or improve PDF testability. We present further transformations which preserve or improve testability. We show that a transformation, claimed to preserve PDF testability, in fact, does not do so. Moreover, the testability improving factor which is a unit of measurement for the quality of testability improving transformations is introduced. Additionally, we present the capabilities of SALT (system forapplication oflocaltransformations), which is a general tool for application of a predefined set of local transformations. The implementation of SALT is described and it is shown how the isomorphism of a “pattern to be searched” and a “matched subcircuit” can be weakened to allow the application of local transformations more frequently. Finally, we confirm the theoretical part of this paper by experimental results obtained by application of the examined local transformations to several benchmark circuits. The effect of these transformations (and combinations of different types of transformations) on PDF testability, size and depth of the transformed circuits is examined and encouraging results are presented. For example, a reduction of up to 90% can be observed for the number of untestable paths.
    Type of Medium: Electronic Resource
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  • 4
    Book
    Book
    Boston [u.a.] :Kluwer Academic Publishers,
    Title: Advanced formal verification /
    Contributer: Drechsler, Rolf
    Publisher: Boston [u.a.] :Kluwer Academic Publishers,
    Year of publication: 2004
    Pages: XXV, 249 S.
    ISBN: 1-402-07721-1
    Type of Medium: Book
    Language: English
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