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  • 1
    Electronic Resource
    Electronic Resource
    Mechanism of low temperature C54 TiSi2 formation bypassing C49 TiSi2: Effect of Si microstructure and Mo impurities on the Ti–Si reaction path (1998)
    Woodbury, NY : American Institute of Physics (AIP)
    Applied Physics Letters 73 (1998), S. 900-902 
    Details
    ISSN: 1077-3118
    Source: AIP Digital Archive
    Topics: Physics
    Notes: X-ray diffraction, high resolution transmission electron microscopy, and resistivity measurements were used to demonstrate a modification of the Ti/Si reaction path consisting of direct nucleation followed by diffusion limited growth of low resistivity C54 TiSi2 without nucleation of high resistivity C49 TiSi2, for the reaction of Ti with Mo doped polycrystalline or Mo doped amorphous Si by rapid thermal processing at 650 °C. We also report the mechanism of early C54 nucleation. We demonstrate that MoSi2 and an unidentified silicide phase lattice matched to C54 TiSi2, with spacings of 4.15 and 2.26 Å, nucleate along the Ti/Si interface at early stages of the reaction and act as templates on which C54 TiSi2 nucleates and grows epitaxially. In contrast, the conventional phase sequence, nucleation and growth of C49 TiSi2 preceding nucleation of C54 TiSi2, was observed for the Ti/Mo doped single crystal (100) Si reaction and for all samples without Mo. © 1998 American Institute of Physics.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1063/1.122032
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    Paper (German National Licenses)
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  • 2
    Electronic Resource
    Electronic Resource
    High-quality germanium photodiodes integrated on silicon substrates using optimized relaxed graded buffers (1998)
    Woodbury, NY : American Institute of Physics (AIP)
    Applied Physics Letters 73 (1998), S. 2125-2127 
    Details
    ISSN: 1077-3118
    Source: AIP Digital Archive
    Topics: Physics
    Notes: The integration of Ge photodetectors on silicon substrates is advantageous for various Si-based optoelectronics applications. We have fabricated integrated Ge photodiodes on a graded optimized relaxed SiGe buffer on Si. The dark current in the Ge mesa diodes, Js=0.15 mA/cm2, is close to the theoretical reverse saturation current and is a record low for Ge diodes integrated on Si substrates. Capacitance measurements indicate that the detectors are capable of operating at high frequencies (2.35 GHz). The photodiodes exhibit an external quantum efficiency of η=12.6% at λ=1.3 μm laser excitation in the photodiodes. The improvement in Ge materials quality and photodiode performance is derived from an optimized relaxed buffer process that includes a chemical mechanical polishing step within the dislocated epitaxial structure. © 1998 American Institute of Physics.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1063/1.122399
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  • 3
    Electronic Resource
    Electronic Resource
    Controlling threading dislocation densities in Ge on Si using graded SiGe layers and chemical-mechanical polishing (1998)
    Woodbury, NY : American Institute of Physics (AIP)
    Applied Physics Letters 72 (1998), S. 1718-1720 
    Details
    ISSN: 1077-3118
    Source: AIP Digital Archive
    Topics: Physics
    Notes: A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge substrates. © 1998 American Institute of Physics.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1063/1.121162
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    Paper (German National Licenses)
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  • 4
    Electronic Resource
    Electronic Resource
    Compatibility of polycrystalline silicon gate deposition with HfO2 and Al2O3/HfO2 gate dielectrics (2002)
    Woodbury, NY : American Institute of Physics (AIP)
    Applied Physics Letters 81 (2002), S. 1288-1290 
    Details
    ISSN: 1077-3118
    Source: AIP Digital Archive
    Topics: Physics
    Notes: Polycrystalline-silicon (poly-Si) gate compatibility issues with HfO2 and Al2O3 capped HfO2 gate dielectrics are reported. It can be generally stated that chemical vapor deposition (CVD) silicon gates using silane deposited directly onto HfO2 results in electrical properties much worse compared to similar HfO2 films using platinum metal gates. However, depositing CVD silicon gates directly onto Al2O3 capped HfO2 showed greater than a 104 times reduction in gate leakage compared to the poly-Si/HfO2 and poly-Si/SiO2 controls of similar electrical thickness. © 2002 American Institute of Physics.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1063/1.1499514
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  • 5
    Electronic Resource
    Electronic Resource
    Visualisation of rapid prototyping (2001)
    Bingley : Emerald
    Rapid prototyping journal 7 (2001), S. 99-114 
    Details
    ISSN: 1355-2546
    Source: Emerald Fulltext Archive Database 1994-2005
    Topics: Mechanical Engineering, Materials Science, Production Engineering, Mining and Metallurgy, Traffic Engineering, Precision Mechanics
    Notes: Discusses a virtual prototyping (VP) system developed for simulation of rapid prototyping processes. It enables a designer to visualise and optimise an RP process with a set of process parameters. The visualisation of a virtually simulated part prior to physical fabrication helps reduce unwanted prototyping iterations. The implementation techniques involved in the development of the VP system and the considerations in selecting virtual reality interfaces are described. The visualisation capability of the system is demonstrated by comparing virtual parts with the corresponding physical prototypes.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1108/13552540110386763
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    Paper (German National Licenses)
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