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  • 1
    Electronic Resource
    Electronic Resource
    Optimisation of submerged arc welding process parameters in hardfacing (1996)
    Springer
    The international journal of advanced manufacturing technology 12 (1996), S. 402-406 
    Details
    ISSN: 1433-3015
    Keywords: Hardfacing ; Neural network ; Optimisation ; Simulated annealing algorithms ; Submerged arc welding
    Source: Springer Online Journal Archives 1860-2000
    Topics: Mechanical Engineering, Materials Science, Production Engineering, Mining and Metallurgy, Traffic Engineering, Precision Mechanics
    Notes: Abstract In this paper, a feedforward neural network is used to model submerged arc welding (SAW) processes in hardfacing. The relationships between process parameters (arc current, arc voltage, welding speed, electrode protrusion, and preheat temperature) and welding performance (deposition rate, hardness, and dilution) are established, based on the neural network. A simulated annealing (SA) optimisation algorithm with a performance index is then applied to the neural network for searching the optimal process parameters. Experimental results have shown that welding performance can be enhanced by using this new approach.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF01186928
    Library Location Call Number Volume/Issue/Year Availability
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    Paper (German National Licenses)
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  • 2
    Electronic Resource
    Electronic Resource
    Residue systolic implementations for neural networks (1995)
    Springer
    Neural computing & applications 3 (1995), S. 149-156 
    Details
    ISSN: 1433-3058
    Keywords: Mixed-radix conversion ; Neural network ; Parallel processing ; Residue number system ; Systolic array
    Source: Springer Online Journal Archives 1860-2000
    Topics: Computer Science , Mathematics
    Notes: Abstract In this work we propose two techniques for improving VLSI implementations for artificial neural networks (ANNs). By making use of two kinds of processing elements (PEs), one dedicated to the basic operations (addition and multiplication) and another to evaluate the activation function, the total time and cost for the VLSI array implementation of ANNs can be decreased by a factor of two compared with previous work. Taking the advantage of residue number system, the efficiency of each PE can be further increased. Two RNS- based array processor designs are proposed. The first is built by look-up tables, and the second is constructed by binary adders accomplished by the mixed- radix conversion (MRC), such that the hardwares are simple and high speed operations are obtained. The proposed techniques are general enough to be extended to cover other forms of loading and learning algorithms.
    Type of Medium: Electronic Resource
    URL: http://dx.doi.org/10.1007/BF01414076
    Library Location Call Number Volume/Issue/Year Availability
    BibTip Others were also interested in ...
    Paper (German National Licenses)
    Fulltext
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