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Evaluation of grain boundary trap states in polycrystalline–silicon thin-film transistors by mobility and capacitance measurements (2002)

Ikeda, H.

[S.l.] : American Institute of Physics (AIP)

Journal of Applied Physics 91 (2002), S. 4637-4645

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ISSN: 1089-7550

Source: AIP Digital Archive

Topics: Physics

Notes: A method for evaluating localized grain boundary (GB) trap states in polycrystalline–silicon thin-film transistors (poly-Si TFTs) is proposed. Field effects in poly-Si TFTs are analyzed by decomposition of the two-dimensional Poisson's equation. This analysis gives the theoretical basis for evaluating the localized GB trap state density. The trap states are evaluated with the GB barrier potential given by the activation energy of the effective mobility and with the surface potential calculated from the capacitance–voltage characteristics in poly-Si TFTs. This evaluating method was applied to several different types of poly-Si TFTs fabricated with excimer laser annealing crystallization processes. This method has succeeded experimentally in eliminating the error effects related to oxide–semiconductor interface trap states and in clarifying that the GB barrier potential has a peak in its gate bias dependence. This method has also elucidated that the GB trap state density has almost the same value independent of the grain size when the hydrogenation efficiency in poly-Si is in the same level between TFTs. The good agreement of the simulated and the measured drain currents confirm the validity of this method. © 2002 American Institute of Physics.

Type of Medium: Electronic Resource

URL: http://dx.doi.org/10.1063/1.1454202

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