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Stacking power MOSFETs for use in high speed instrumentation (1992)

Baker, R. J. ; Johnson, B. P.

[S.l.] : American Institute of Physics (AIP)

Review of Scientific Instruments 63 (1992), S. 5799-5801

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ISSN: 1089-7623

Source: AIP Digital Archive

Topics: Physics , Electrical Engineering, Measurement and Control Technology

Notes: A reliable circuit configuration is described for stacking power metal–oxide semiconductor field effect transistors (MOSFETs). The resulting circuit has a hold off voltage N times larger than a single power MOSFET, where N is the number of power MOSFETs used. The capability to switch higher voltages and thus greater amounts of power, into a 50 Ω load, in approximately the same time as a single device is realized. Design considerations are presented for selecting a power MOSFET. Using the design method presented, a 1.4 kV pulse generator, into 50 Ω, with a 2 ns rise time and negligible jitter is designed.

Type of Medium: Electronic Resource

URL: http://dx.doi.org/10.1063/1.1143366

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