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Transition Test Patterns Generation for BIST Implemented in ASIC and FPGA (2008)

Abraitis, Vidas ; Tamoševičius, Žydrūnas

s.l. ; Stafa-Zurich, Switzerland

Solid state phenomena Vol. 144 (Sept. 2008), p. 214-219

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ISSN: 1662-9779

Source: Scientific.Net: Materials Science & Technology / Trans Tech Publications Archiv 1984-2008

Topics: Physics

Notes: Transition delay testing of sequential circuits in a clocked environment is analyzed.There are presented two test pattern generator methods for built in self testing of the circuitimplemented as Application Specific Integrated Circuit (ASIC) and Field Programmable GateArray (FPGA) of Virtex family. Cellular automaton and Linear Feedback Shift Register (LFSR)structures are used for test sequence generation. The circuits are tested as the black boxes underTransition fault model. Experimental results of the test pattern generation methods are presentedand analyzed. Results compared with exhaustive test of transition faults for ASICs andprogrammable integrated circuits with given configuration

Type of Medium: Electronic Resource

URL: http://www.tib-hannover.de/fulltexts/2011/0528/02/24/transtech_doi~10.4028%252Fwww.scientific.net%252FSSP.144.214.pdf

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