Bibliothek

Notizen: Oxidation of the Si overlayer in silicon separated by oxygen (SIMOX) is expected to form oxidation stacking faults (OSF) since this process generates Si interstitials into the active Si layer. In spite of this process, recent experiments reveal that the density of OSF is very low. A possible mechanism to explain the absence of OSF in SIMOX is that Si interstitials rejected from the Si-overlayer/SiO2 interface could react with the SiO2 of the buried layer to form SiO molecules (Si+SiO2=2SiO). These species, which can diffuse four orders of magnitude faster than Si through the SiO2 buried layer, are recombined by the reverse reaction at the back interface due to the absence of Si-interstitial supersaturation. Since the activation energy for this process is 4.4 eV, OSF can be generated if the Si overlayer is subjected to a preoxidation treatment that introduces a high density of stacking fault (SF) nucleation sites, because the activation energy for heterogeneous generation of OSF is only 2.3 eV. In this case 0.21×10−3 of Si interstitials are incorporated in OSF over the total Si atoms that are consumed during the oxidation. This value agrees with the proportion of Si interstitials incorporated in OSF when the SiO2 buried layer is replaced by a Si3N4 buried layer since this layer is a barrier for the Si-interstitial migration to the substrate. The value 0.21×10−3 is very close to the expected theoretical value revealing that almost all the Si interstitials were captured by the OSF.

Notizen: The generation of dislocations in silicon implanted by oxygen (SIMOX) is studied by transmission electron microscopy. In an effort to separate the effects of displacement damage caused by ion implantation from the dynamic structural transformation which occurs due to the insertion of oxygen into the lattice, two special experiments were designed. The first consisted of a series of low dose oxygen implantations in which the energy was either ramped up or down in small steps. This served to expand the region in which oxygen was implanted, permitting a more detailed study of the defects. The second experiment involved the implantation of oxygen into a (111) wafer in order to study the influence of the crystallographic orientation on the generation of dislocations. Both experiments reveal the important role of the surface in the generation of dislocations. It is concluded that most of the threading dislocations are formed during the high-temperature anneal and have their origin in a defect-rich zone near the surface. These defects are attributed to Si-interstitial migration to the surface which results from the formation of SiO2. Consequently, epitaxial growth takes place on the surface and due to the growth defects generated there, dislocations are extended to the Si overlayer during the high-temperature annealing. Dislocations are also formed in the Si overlayer near the interface with the SiO2 buried layer. These dislocations are pinned by the SiO2 precipitates and are either consumed or dragged by them to the oxide interface during subsequent high-temperature annealing. The effect of surface contamination on the generation of dislocations in the early stage of implantation is discussed and factors which yield a better quality SIMOX material are presented.

Notizen: Two-dimensional growth of GaAs on (100) silicon has been achieved by combining laser-assisted growth and modulation molecular-beam epitaxy techniques. The misfit dislocations were shown to form a regular cross-grid with satellite reflections characteristic of a two-dimensional homoepitaxial growth as also revealed by the perfection of the moiré patterns of the GaAs/Si interface. The few antiphase domains generated at the interface were observed to annihilate very fast. The top surface of GaAs was free of antiphase domains. Planar defects such as stacking faults and microtwins are also eliminated.

Notizen: The morphology of polycrystalline films grown by low-pressure chemical-vapor deposition (LPCVD) is investigated by transmission electron microscopy (TEM) as a function of the film thickness, the deposition pressure, and the level of contamination. An orientation filtering mechanism, due to the growth-velocity competition in the early stage of growth, is responsible for the preferred orientation of the films. The size of the crystallites, the surface roughness, and the type of the structural defects are investigated by combined cross-sectional and plane-view TEM analysis. In polycrystalline silicon thin-film transistors (TFTs), the influence of surface roughness scattering on the mobility is investigated by measuring the effective electron mobility under high effective normal field at 295 and 77 K. Although the surface curvature is increased when the deposition pressure is decreased, the surface roughness scattering is constant in the deposition pressure range from 40 to 0.5 mTorr. By decreasing the deposition pressure from 40 to 10 mTorr, although the grain size increases, the TFT performance degrades due to the following factors: (a) the increase of the grain-boundary trap density which is related to the change of the mode of growth at 10 mTorr; and (b) the increase of impurity contamination in the environment of the LPCVD system with constant silane flow rate at all pressures. At a deposition pressure of 0.5 mTorr the TFT performance is improved indicating that the grain size is the prevailing key factor.

Notizen: We present results on the growth and shrinkage of oxidation stacking faults in silicon implanted with oxygen (SIMOX) structures and compare them with bulk silicon. The growth results show an enhanced length of the faults in SIMOX. Using the silicon direct bonding technique, we determine the critical silicon film thickness for which the length of the faults becomes the same as in bulk silicon. The shrinkage behavior of the faults during annealing in inert ambient was also studied and similar results for both materials were obtained. From these experiments we get insight into the fundamental properties of silicon self-interstitials.

Notizen: A systematic study of the growth of high-quality films of GaAs on Si substrates has been performed for applications in devices, particularly in optoelectronic devices for cointegration in optical interconnects. The effort for optimized active layers was approached through the separate optimization of substrate preparation, growth time parameters, and postgrowth treatment. In particular, the study of growth involved the investigation of the effect of silicon substrate orientation, post-growth treatment, as well as multilayer and, especially, silicon buffer layers. For quantification of film quality, a number of characterization methods were used both in situ: reflected high-energy electron diffraction (RHEED); and ex situ: optical, electrical [current versus voltage (I-V), capacitance versus voltage (C-V), deep-level transient spectroscopy (DLTS), Hall], transmission electron microscopy (TEM), scanning electron microscopy (SEM), electron channeling patterns, x-ray double-crystal diffractometry (DDX). Schottky diodes, p-n heterojunctions, and metal-semiconductor-metal photoconductors/photodetectors (MSM PC/PDs), field-effect transistors, and high electron mobility transistors were fabricated on these films. The most crucial parameter for device operation and film uniformity is the complete absence of antiphase boundaries which increase leakage, degrade mobilities, and seem to result in interface two-dimensional electron gas in substrates misoriented toward 〈110〉.Absolutely smooth GaAs morphology is obtained using a molecular-beam epitaxy grown Si buffer layer and controlling the orientation of the GaAs film so that the [110] direction is parallel to the 〈110〉 misorientation direction of the vicinal (001) substrates. This can be ensured by an As4 prelayer grown at 350 °C. A double 2×1 domain Si surface seems to be preferable, as it allows the choice of such a GaAs orientation. GaAs growth is then 2D from the very early stages of growth, following the homogeneous nucleation of 3D GaAs islands, resulting in the complete elimination of planar faults. A perfectly regular displacement-type moiré pattern in the GaAs/Si interface is then observed. GaAs buffers on Si with an MBE Si buffer exhibit high resistivity, probably due to growth on contamination-free surfaces. The lowest ever reported 1 μm DDX full width at half-maximum of 255 arcsec was observed for such a GaAs/Si/Si layer. Nevertheless, accurate TEM dislocation counts indicate a dislocation density in the low 108 cm−2 range. In addition, a saturation in DDX FWHM values appears for an epilayer thickness of about 2 μm. This may be related to values being limited by wafer bowing or it may indeed reflect a limit in film quality. Post-growth rapid thermal annealing results in redistribution of dislocations in a nonuniform way with most congregating in small areas of high dislocation density, leaving large areas with low dislocation density.It is concluded that by either increasing the GaAs epilayer thickness or the sample temperature one produces a residual compressive stress that forces the threading dislocations to slip, thus reducing their density by reactions that become moreprobable with proximity. The residual dislocation density of about 108 cm−2 is attributed partly to threading dislocation generation during the early stages of epitaxy and only partly to generation from tensile thermal stress during cooling. Schottky diodes on GaAs/Si break down at the same or similar voltages as on homoepitaxial material. MSM PC/PDs have comparable dark dc leakage currents, somewhat lower dc photoresponse, and comparable rise and fall times, and metal-semiconductor field-effect transistors (1.5 μm gate length) fabricated on GaAs/Si/Si show a maximum extrinsic transconductance of 230 mS/mm, actually somewhat higher than for homoepitaxial devices. Thus, device results allow us to claim that we have achieved a technology that leads to heteroepitaxial GaAs/Si films which compare in performance to homoepitaxial GaAs/GaAs within about 10% for applications in most devices. The use of an MBE Si buffer layer, in addition to improving the quality of the GaAs layer, results in a reduction of a processing temperature by at least 100 °C. This reduction, along with the elimination of the step-doubling processing step, makes GaAs film growth compatible to unmetallized fully processed complementary metal-oxide-semiconductor (CMOS) Si wafers.

Notizen: The structure and the morphology of crystallized amorphous silicon (α-Si) films which were deposited on glass and annealed in a conventional furnace or by rapid thermal process (RTP) are studied using transmission electron microscopy (TEM). The ellipsoidal shape of the grains is attributed to the fast solid-state crystallization along the two mutually perpendicular 〈112〉 and 〈110〉 crystallographic directions. The growth is solely based on the twin formation. The stability of the microtwins was studied by RTP and in situ TEM heating experiments. The effect of the film thickness on the preferred orientation of the grains is discussed. Very thin films exhibit (111) preferred orientation due to the strongly anisotropic rate of growth of the nuclei, which imposes an orientation filtering due to a growth velocity competition. The mode of growth of these films is compared with poly-Si films grown by low-pressure chemical-vapor deposition.

Notizen: Amorphization of 6H-SiC with 200 keV Ge+ ions at room temperature and subsequent ion-beam-induced epitaxial crystallization (IBIEC) with 300 keV Si+ ions at 480 °C have been studied by Rutherford backscattering spectrometry/channeling and transmission electron microscopy analysis. Experimental results on amorphous layer thicknesses have been compared with trim calculations in association with the critical energy density model. Density changes during amorphization have been observed by step height measurements. Particular attention has been directed to the crystal quality and a possible polytype transformation during the IBIEC regrowth. The IBIEC process consists of two stages and results in a multilayer structure. In the initial phase an epitaxial growth of 6H-SiC has been obtained. With increasing IBIEC dose the epitaxial growth changes to columnar growth and is stopped by polycrystallization of 3C polytype in the near-surface region. © 1995 American Institute of Physics.

Notizen: A gold layer one order of magnitude thinner than the thickness of an amorphous silicon layer in intimate contact leads to the dissolution of the amorphous silicon into the liquid and the subsequent precipitation of crystalline Si as the liquid phase propagates into the amorphous phase at above eutectic temperatures. The crystalline Si precipitate has grain sizes of the order of 6 μm. The Si/Au liquid is very sensitive to constitutional supercooling and subsequent crystallization.

Notizen: Aluminum carbide precipitates are formed after Al ion implantation with dose 3×1017 cm−2 at 500 °C into single crystalline 6H–SiC. The aluminum carbide (Al4C3) precipitates are in epitaxial relation with 6H–SiC matrix, having the following orientation relation, [0001]6H–SiC//[0001]Al4C3, and [112¯0]6H–SiC//[112¯0]Al4C3, as transmission electron microscopy reveals. The aluminum carbide appears around the maximum of the Al depth distribution. Silicon precipitates were also detected in the same zone. © 1999 American Institute of Physics.